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1/24 october 2004 VN920-E vn920b5-e / vn920so-e high side driver rev. 1 table 1. general features cmos compatible input proportional load current sense shorted load protection undervoltage and overvoltage shutdown overvoltage clamp thermal shutdown current limitation protection against loss of ground and loss of v cc very low stand-by power dissipation reverse battery protection (*) in compliance with the 2002/95/ec european directive description the VN920-E, vn920b5-e, vn920so-e is a monolithic device made by using stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). figure 1. package active current limitation combined with thermal shutdown and automatic restart protect the device against overload. the device integrates an analog current sense output which delivers a current proportional to the load current. device automatically turns off in case of ground pin disconnection. table 2. order codes note: (*) see application schematic at page 9. type r ds(on) i out v cc VN920-E vn920b5-e vn920so-e 16m ? 30 a 36 v pentawatt p 2 pak so-16l package tube tape and reel pentawatt VN920-E - p 2 pak vn920b5-e vn920b5tr-e so-16l vn920so-e vn920sotr-e
VN920-E / vn920b5-e / vn920so-e 2/24 figure 2. block diagram table 3. absolute maximum ratings symbol parameter value unit pentawatt p 2 pak so-16l v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 21 a i in dc input current +/- 10 ma v csense current sense maximum voltage -3 +15 v v v esd electrostatic discharge (human body model: r=1.5k ? ; c=100pf) - input - current sense - output - v cc 4000 2000 5000 5000 v v v v e max maximum switching energy (l=0.25mh; r l =0 ? ; v bat =13.5v; t jstart =150oc; i l =45a) 364 352 mj p tot power dissipation t c 25c 96.1 96.1 8.3 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c undervoltage overtemperature v cc gnd input output overvoltage current limiter logic driver power clamp v cc clamp v ds limiter detection detection detection k i out current sense
3/24 VN920-E / vn920b5-e / vn920so-e figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins figure 4. current and voltage conventions table 4. thermal data ( 1 ) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m thick). ( 2 ) when mounted on a standard single-sided fr-4 board with 6cm 2 of cu (at least 35 m thick). ( 3 ) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m thick) connected to all v cc pins. ( 4 ) when mounted on a standard single-sided fr-4 board with 6cm 2 of cu (at least 35 m thick) connected to all v cc pins. symbol parameter value unit pentawatt p 2 pak so-16l r thj-case thermal resistance junction-case max 1.3 1.3 c/w r thj-lead thermal resistance junction-lead max 15 c/w r thj-amb thermal resistance junction-ambient max 61.3 51.3 ( 1 ) 65 ( 3 )c/w 37 ( 2 ) 48 ( 4 )c/w 5 4 3 2 1 v cc gnd input c sense output pentawatt 3 2 1 4 5 v cc gnd input c sense output p 2 pak v cc output output output output v cc output output v cc n.c. n.c. c sense input v cc gnd n.c. 1 8 9 16 so-16l connection / pin current sense n.c. output input floating x x x to ground through 1k ? resistor x through 10k ? resistor i s i gnd v cc v cc v sense output i out current sense i sense input i in v in v out gnd v f
VN920-E / vn920b5-e / vn920so-e 4/24 electrical characteristics (8v 5/24 VN920-E / vn920b5-e / vn920so-e electrical characteristics (continued) table 8. v cc - output diode table 9. protections (see note 1) note: 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sign als must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. table 10. current sense (9v v cc 16v) (see fig. 5) note: 2. current sense signal delay after positive input slope. symbol parameter test conditions min. typ. max. unit v f forward on voltage -i out =2a; t j =150c 0.6 v symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c i lim dc short circuit current v cc =13v 5v8v; i out =10a; r sense =10k ? 2 4 v v v senseh sense voltage in overtemperature conditions v cc =13v; r sense =3.9k ? 5.5 v r vsenseh analog sense output impedance in overtemperature condition v cc =13v; t j >t tsd ; output open 400 ? t dsense current sense delay response to 90% i sense (see note 2) 500 s
VN920-E / vn920b5-e / vn920so-e 6/24 figure 5. i out /i sense versus i out figure 6. switching characteristics (resistive load r l =1.3 ? ) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3000 3500 4000 4500 5000 5500 6000 6500 min.tj=-40c max.tj=-40c min.tj=25...150c max.tj=25...150c typical value i out (a) i out /i sense v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) i sense t t 90% t d(off) input t 90% t d(on) t dsense
7/24 VN920-E / vn920b5-e / vn920so-e table 11. truth table table 12. electrical transient requirements on v cc pin conditions input output sense normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overvoltage l h l l 0 0 short circuit to gnd l h h l l l 0 (t j t tsd ) v senseh short circuit to v cc l h h h 0 < nominal negative output voltage clamp ll 0 iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 ? 2 +25 v +50 v +75 v +100 v 0.2 ms 10 ? 3a -25 v -50 v -100 v -150 v 0.1 s 50 ? 3b +25 v +50 v +75 v +100 v 0.1 s 50 ? 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 ? 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 ? iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5ceee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
VN920-E / vn920b5-e / vn920so-e 8/24 figure 7. waveforms sense input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc sense input sense load current load current load current overtemperature input sense t tsd t r t j load current v ov v ovhyst v cc > v usd short to ground input load current sense load voltage input load voltage sense load current 9/24 VN920-E / vn920b5-e / vn920so-e figure 8. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device?s datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k ?) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input line is also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input pin is to leave it unconnected, while unused sense pin has to be connected to ground pin. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 20ma; v oh c 4.5v 5k ? r prot 65k ? . recommended r prot value is 10k ?. v cc gnd output d gnd r gnd d ld c +5v r prot v gnd input current sense r sense r prot
VN920-E / vn920b5-e / vn920so-e 10/24 figure 9. off state output current figure 10. high level input current figure 11. input clamp voltage figure 12. on state resistance vs t case figure 13. on state resistance vs v cc figure 14. input high level -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 1 2 3 4 5 6 7 8 9 il(off1) (ua) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 5 10 15 20 25 30 35 40 45 50 ron (mohm) iout=10a vcc=8v; 36v 5 10152025303540 vcc (v) 0 5 10 15 20 25 30 35 40 45 50 ron (mohm) tc= - 40oc tc= 25oc tc= 150oc -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v)
11/24 VN920-E / vn920b5-e / vn920so-e figure 15. input low level figure 16. turn-on voltage slope figure 17. overvoltage shutdown figure 18. input hysteresis voltage figure 19. turn-off voltage slope figure 20. i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 250 300 350 400 450 500 550 600 650 700 dvout/dt(on) (v/ms) vcc=13v rl=1.3ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 50 100 150 200 250 300 350 400 450 500 550 dvout/dt(off) (v/ms) vcc=13v rl=1.3ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 10 20 30 40 50 60 70 80 90 100 ilim (a) vcc=13v
VN920-E / vn920b5-e / vn920so-e 12/24 figure 21. p 2 pak maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 ? in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. 1 10 100 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
13/24 VN920-E / vn920b5-e / vn920so-e figure 22. so-16l maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 ? in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. 1 10 100 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
VN920-E / vn920b5-e / vn920so-e 14/24 so-16l thermal data figure 23. so-16l pc board figure 24. so-16l r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 41mm x 48mm, pcb thickness=2mm, cu thickness=35 m, copper areas: 0.5cm 2 , 6cm 2 ). 40 45 50 55 60 65 70 01234567 pcb cu heatsink area (cm^2) rth j-amb (c/w)
15/24 VN920-E / vn920b5-e / vn920so-e p 2 pak thermal data figure 25. p 2 pak pc board figure 26. p 2 pak r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 60mm x 60mm, pcb thickness=2mm, cu thickness=35 m, copper areas: 0.97cm 2 , 8cm 2 ). 30 35 40 45 50 55 0246810 pcb cu heatsink area (cm^2) rthj_amb (c/w) tj-tamb=50c
VN920-E / vn920b5-e / vn920so-e 16/24 figure 27. p 2 pak thermal impedance junction ambient single pulse figure 28. thermal fitting model of a single channel hsd in p 2 pak pulse calculation formula table 13. thermal parameter 0.01 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zt h (c /w) 0.97 cm 2 6 cm 2 t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj area/island (cm 2 )0.976 r1 (c/w) 0.02 r2 (c/w) 0.1 r3 ( c/w) 0.22 r4 (c/w) 4 r5 (c/w) 9 r6 (c/w) 37 22 c1 (w.s/c) 0.0015 c2 (w.s/c) 0.007 c3 (w.s/c) 0.015 c4 (w.s/c) 0.4 c5 (w.s/c) 2 c6 (w.s/c) 3 5 th r th z thtp 1 ? () + ? = where t p t ? =
17/24 VN920-E / vn920b5-e / vn920so-e figure 29. so-16l thermal impedance junction ambient single pulse figure 30. thermal fitting model of a single channel hsd in so-16l pulse calculation formula table 14. thermal parameter 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) 0.5 cm 2 6 cm 2 t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj area/island (cm 2 )0.56 r1 (c/w) 0.02 r2 (c/w) 0.1 r3 ( c/w) 2.2 r4 (c/w) 12 r5 (c/w) 15 r6 (c/w) 35 20 c1 (w.s/c) 0.0015 c2 (w.s/c) 7.00e-03 c3 (w.s/c) 1.50e-02 c4 (w.s/c) 0.14 c5 (w.s/c) 1 c6 (w.s/c) 5 8 th r th z thtp 1 ? () + ? = where t p t ? =
VN920-E / vn920b5-e / vn920so-e 18/24 package mechanical table 15. so-16l mechanical data figure 31. so-16l package dimensions symbol millimeters min typ max a 2.35 2.65 a1 0.10 0.30 b 0.33 0.51 c 0.23 0.32 d 10.10 10.50 e 7.40 7.60 e1.27 h 10.00 10.65 h 0.25 0.75 l 0.40 1.27 k0o 8o ddd 0.10 package weight 0.4gr. (typ.)
19/24 VN920-E / vn920b5-e / vn920so-e package mechanical table 16. pentawatt (vertical) mechanical data figure 32. pentawatt (vertical) package dimensions symbol millimeters min typ max a 4.8 c 1.37 d2.4 2.8 d1 1.2 1.35 e 0.35 0.55 f 0.8 1.05 f1 1 1.4 g 3.2 3.4 3.6 g1 6.6 6.8 7 h2 10.4 h3 10.05 10.4 l 17.85 l1 15.75 l2 21.4 l3 22.5 l5 2.6 3 l6 15.1 15.8 l7 6 6.6 m4.5 m1 4 diam. 3.65 3.85
VN920-E / vn920b5-e / vn920so-e 20/24 package mechanical table 17. p 2 pak mechanical data figure 33. p 2 pak package dimensions symbol millimeters min typ max a 4.30 4.80 a1 2.40 2.80 a2 0.03 0.23 b 0.80 1.05 c 0.45 0.60 c2 1.17 1.37 d 8.95 9.35 d2 8.00 e 10.00 10.40 e1 8.50 e 3.20 3.60 e1 6.60 7.00 l 13.70 14.50 l2 1.25 1.40 l3 0.90 1.70 l5 1.55 2.40 r0.40 v2 0o 8o package weight 1.40 gr (typ) p010r
21/24 VN920-E / vn920b5-e / vn920so-e figure 34. so-16l tube shipment (no suffix) figure 35. so-16l tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 50 bulk q.ty 1000 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 a c b reel dimensions all dimensions are in mm. base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
VN920-E / vn920b5-e / vn920so-e 22/24 figure 36. p 2 pak tube shipment (no suffix) figure 37. p 2 pak tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 50 bulk q.ty 1000 tube length ( 0.5) 532 a 18 b 33.1 c ( 0.1) 1 c b a reel dimensions all dimensions are in mm. bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 16 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
23/24 VN920-E / vn920b5-e / vn920so-e revision history table 18. revision history date revision description of changes oct. 2004 1 - first issue.
VN920-E / vn920b5-e / vn920so-e 24/24 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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